In order to improve the reliability of star sensors, their hardware system design often requires the use of engineering design and verification ideas. According to the general task requirements of the star sensor, the hardware system of the star sensor is composed of the electrical architecture of the programmable logic device CPLD and the core processor DSP, the image sensor of progressiveness CMOS technology and the optical front end of the optical lens. The entire hardware system should meet the physical, electrical, and computational power requirements of star sensor.
The hardware system of star sensors generally consists of optical and electrical systems.
Figure 3-1 Schematic diagram of star sensor framework
In this scheme, CPLD is responsible for image acquisition and storing the collected image data in SRAM; The memory SRAM is responsible for caching the real-time collected star map data; DSP completes the initialization of the system, configures IBIS5 through a 16 bit parallel bus, and reads image data from SRAM through EMIFA port and CPLD, saving it to SDRAM. Finally, the star pattern recognition matching algorithm is executed. FLASH is mainly used to store catalog data and code during DSP loading.
1) Optical lens selection
The physical image of the lens is shown in Figure 3-2. This lens has the advantages of light weight, small size, large field of view, and relatively small aperture. Focal length 34mm, lens aperture 25mm, relative aperture F # 1.4, field of view 27.8 ° × 20.8 °, weight 87g, volume φ 33.5mm × 38.2mm;
Figure 3-2 Physical image of optical lens
2) Selection of Image Sensor (CMOS)
CMOS image sensor, as shown in Figure 3-3. This chip integrates functions such as analog image acquisition and AD conversion, without the need for complex driver circuits. It has the advantages of light weight, small size, low power consumption, large fill factor, high quantum efficiency, strong radiation resistance, and easy to use. The pixel size of the image sensor is 6.7um. Under normal operating mode, the power consumption is only 175mW, and the maximum frame rate can reach 27.5fps. Its maximum resolution is 1280 × 1024. At the same time, it has the ability to randomly open windows, making it very flexible in practical applications. In terms of data communication, there are 16bit parallel bus communication mode and SPI serial communication mode, and users can choose according to their own needs by configuring the registers of the image sensor.
Figure 3-3 Physical image of CMOS image sensor
The star sensor needs to complete CMOS image sensor driver, image cache, communication with DSP unit, two out of three loading during DSP Bootload, and image preprocessing work. The above are mostly logical operations, with fewer involving large-scale algorithmic operations.
1) Selection of DSP (core processor of star sensor)
The selected DSP is a C6000 series DSP from TI company, with a main frequency of up to 300MHz and a single instruction execution cycle of about 3ns. It has strong floating-point computing ability and supports up to 128 interrupts. On chip with two 32-bit external memory interfaces EMIFA and EMIFB, it can communicate directly with SDRAM, SRAM, and FLASH through appropriate configuration, with a maximum external addressing space of 256MB × 32bit. This DSP has rich interface resources and supports communication modes such as UART, SPI, USB, I2C, etc. It also supports sleep mode to reduce system power consumption. The 1.0V standby power consumption is only 7mW.
2) Programmable Logic Device: Selection of CPLD
CPLD has the advantages of low power consumption, requiring fewer peripheral auxiliary circuits, being able to burn and write multiple times, and not losing power when powered down. At the same time, it can meet the above design requirements. Based on the above considerations, the programmable logic device inherits the selection of the original prototype and uses the CoolRunner II series CPLD produced by Xilinx company. This CPLD has a total of 256 pins and 202 I/O ports, and adopts a new CMOS integrated process. It has the advantages of low power consumption, high performance, and can greatly reduce the power consumption of the entire star sensor system.
3) Memory selection
SRAM uses 1M × The 8-bit IS62WV20488BLL is configured on the CPLD end, and this chip has extremely low power consumption. The power consumption under normal operation is 36mW, and the standby power consumption is 12uW, meeting the data caching requirements of CPLD.
SPI FLASH uses M25P80 with a capacity of 8Mbits, mainly used for storing DSP programs and catalog data. M25P80 is a serial SPI FLASH with advantages such as small size and simple connection. The maximum read clock speed is 40MHz, data storage is at least 20 years, and each sector can withstand 100000 write cycles, meeting the requirements of this design.
SDRAM selects two 16 bit 256Mbits MT48LC16M16A2 configured on the EMIFB port of the DSP, providing 64MByte of external data storage space for the DSP, fully meeting the external memory expansion requirements of the star sensor DSP.
4) Selection of power supply
The voltage required on this star sensor is as follows: a) CMOS image sensor: 4.5V, 3.3V; b) CPLD: 3.3V, 1.8V; c) DSP: 3.3V, 1.2V; d) SDRAM, FLASH, SRAM: 3.3V;
In addition, an anti surge circuit structure is installed at the input end of the external power supply to prevent excessive transient current when the system is powered on, in order to improve the reliability and stability of the system circuit.
1) Design of Interface Circuit between CPLD and CMOS Image Sensors
Figure 3-4 Schematic diagram of the interface circuit between CPLD and CMOS image sensor
2) Design of Interface Circuit between CPLD and SRAM
Figure 3-5 Schematic diagram of the interface circuit between CPLD and SRAM
3) Design of Interface Circuit between CPLD and DSP
Figure 3-6 Schematic diagram of the interface circuit between DSP and CPLD image sensor
4) Design of CPLD and FLASH Interface Circuit
Figure 3-7 Schematic diagram of the interface circuit between CPLD and three chip FLASH
5) Design of Interface Circuit between DSP and CMOS Image Sensors
Figure 3-8 Schematic diagram of the interface circuit between DSP and CMOS image sensor
6) Design of DSP and SDRM Interface Circuit
Figure 3-9 Schematic diagram of the interface circuit between DSP and SDRAM image sensor
7) Design of Interface Circuit between DSP, UART, BOOT
The UART module of DSP is mainly used for communication between DSP and the upper computer, facilitating instruction interaction between the star sensor system and the integrated electronic system. The BOOT module of DSP is used for loading DSP programs.
After verification, the technical specifications of the star sensor hardware should meet the requirements of the preset specifications.
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